Period generating device

ABSTRACT

The present invention makes it possible that a period generating device required to operate at high rate can be implemented as an IC of a CMOS structure. Shift registers each operating as a pipeline are provided at the previous stage and the subsequent stage to a period memory for storing period data, respectively. Each shift register is constituted by a plurality of flip-flops, and a switching circuit is provided at the previous stage to each of the flip-flops. The switching circuits are controlled to provide a cascade connection of the flip-flops to perform a shift operation in response to a reference clock applied to the trigger terminals of the flip-flops only during the time interval that coincidence detecting means outputs a coincidence signal, which detects a coincidence between a period data and an output from a counter for counting the reference clock. As a result, when the coincidence detecting means does not output the coincidence signal, each shift register maintains data stored therein, whereas when the coincidence signal is outputted, each shift register performs a shift operation reliably in response to the reference clock.

TECHNICAL FIELD

The present invention relates to a period generating device which isused in a semiconductor device testing apparatus (commonly called ICtester) for testing a semiconductor device, particularly, asemiconductor integrated circuit element (hereinafter referred to as IC)which is a typical example of the semiconductor devices, and generates apulse signal having a test period which is previously set, that is, apulse having a period with which a test pattern is generated.

BACKGROUND ART

First, a semiconductor device testing apparatus (hereafter referred toas IC tester) in which a period generating device of this type is usedwill be briefly described with reference to FIG. 4 which shows a generalarrangement of a conventional IC tester. The IC tester, generallydesignated by reference numeral 1, comprises, roughly speaking, a timinggenerator (TMG GEN) 2 for generating various kinds of timing signals, apattern generator (PTN GEN) 3 supplied from the timing generator 2 witha timing signal (TMG SIG), that is, a period signal (PRD SIG) definingthe period with which a test pattern is generated and for generating apredetermined test pattern data (TEST PTN DATA) in accordance with theperiod signal, a waveform generator (WAVE GEN) 4 for generating a testpattern signal (TEST PTN SIG) having real waveforms required to test anIC 6 to be tested based on the test pattern data supplied from thepattern generator 3, and a logical comparator (LG COMPA) 5 to which aresponse output signal (RPS OUT SIG) from the IC 6 to be tested and anexpected pattern data (EP PTN DATA) generated from the pattern generator3 are supplied.

A response output signal outputted from the IC 6 to be tested inresponse to a test pattern signal applied from the waveform generator 4is inputted to the logical comparator 5 wherein it is logically comparedwith an expected value pattern data outputted from the pattern generator3. When the response output signal does not coincide with the expectedvalue pattern data, the logical comparator 5 generates a signalindicating that there is an anti-coincidence therebetween so that adecision is rendered that the IC to be tested contains a defectiveportion (failure) or portions.

The period of a period signal outputted from the timing generator 2 isdefined by timing set data (TMG SET DATA) TS which is fed from thepattern generator 3 to the timing generator 2. That is, the timinggenerator 2 outputs a period signal the period of which is defineddepending upon the timing set data TS outputted from the patterngenerator 3, and the pattern generator 3 outputs test pattern data inaccordance with the period of that period signal.

A general arrangement of a conventional period generating device whichdefines the period of a period signal will now be described withreference to FIG. 5. As shown in FIG. 5, a period generating device 10is provided within the timing generator 2, and may comprise a periodmemory (PRD MEM) 11 in which period data are previously stored, acounter (CTR) 12 for counting a reference clock (REF CLK) PC used in theperiod generating device 10, and coincidence detecting means 13 foroutputting a coincidence detection signal J when a count value of thecounter 12 coincides with period data outputted from the period memory11.

The timing set data TS outputted from the pattern generator 3 isinputted to an address terminal of the period memory 11 thereby readingout of the period memory 11 period data corresponding to respectivetiming set data TS. A period data which is read out of the period memory11 corresponds to the number of reference clocks PC. For example, if thereference clock PC has a frequency of 100 MHz, one period of thereference clock is equal to 10 nanoseconds (nsec). Accordingly, when aperiod data read out of the period memory 11 in response to the inputtedtiming set data TS is equal to, for example, "2" (which indicates thatthe number of the reference clocks is equal to 2), the outputted periodsignal has a period of 2×10 (=20) nsec. In such manner, a numericalvalue of the period data read out of the period memory 11 is convertedinto a period (time).

In the example shown in FIG. 5, the period generating device 10 is soarranged that a part of the coincidence detection signal J outputtedfrom the coincidence detecting means 13 is fed through an OR circuit 14to a load input terminal LD of the counter 12. Accordingly, the counter12 is initialized each time the coincidence detecting means 13 outputs acoincidence detection signal J, and the initialization and the detectionof coincidence are repeated so that the coincidence detection signal Jshown in FIG. 6D is outputted as a period signal.

The operation of the period generating device 10 begins with an input ofa period generation start signal (PRD GEN START SIG) to the other inputof the OR circuit 14. The period generation start signal is a signalobtained by detecting a rise (leading edge) of a period generationsignal supplied from the pattern generator 3. Normally, a periodgenerating operation is performed when the period generation signalassumes "H (high logical level)", and hence the rise of this "H" signalis detected. When the period generating operation is started, thecounter 12 which operates in accordance with the reference clock PC usedin the period generating device 10 is set to "1" (initialized state),and counts up in synchronism with the reference clock PC. A coincidencebetween a count in the counter 12 and period data outputted from theperiod memory 11 is detected by the coincidence detecting means 13, andthe detected coincidence signal serves as a period signal as describedabove. Assuming that the period data is "2" as mentioned above, thecoincidence of the count with the period data is detected each time thecount in the counter 12 reaches 2. Consequently, the period of a periodsignal generated has a length in time corresponding to the sum of 2pulses in the reference clock signal. When the reference clock signal PChas a frequency of 100 MHz, the period is equal to 2×10 (=20) nsec asdiscussed above.

While not shown, an AND of the period signal and the reference clock istaken in an AND circuit the output of which serves as a period clock LTshown in FIG. 6E. As described above, each time the coincidence signalis outputted, the counter 12 is set to "1" (which corresponds to thatthe number of the reference clock is equal to 1), or is initialized, andsubsequently the same operation is repeated.

It will be noted that the construction of the period generating device10 is shown in a simplified manner in FIG. 5 in order to explain amechanism of generating a period clock LT. However, in actuality, theperiod clock LT must be generated at high rate or speed. Therefore, itis impossible to achieve a high rate operation by the above-mentionedcircuit arrangement that the timing set data TS is read out of thepattern generator 2. For this reason, in the prior art is used such anarrangement as shown in FIG. 7 that two shift registers 18 and 19, eachcomprising a series of flip-flops which operate as a pipeline, areprovided at the previous stage and the subsequent stage to the periodmemory 11, respectively, and each of the stages (flip-flops) of theprevious stage shift register 18 has timing set data TS previouslystored therein. With such arrangement, each time the coincidence signalJ is outputted, the both shift registers 18 and 19 are driven so thatthe timing set data TS and the period data are shifted one stage (oneflip-flop) by one stage, which enables a quick-access to the periodmemory 11 as well as enables the read-out output, namely, the perioddata to supply to the coincidence detecting means 13 at high rate orspeed.

In case the period generating device 10 is manufactured in the form ofintegrated circuit (IC), to construct the circuit arrangement of the ICin the form of a CMOS (complementary MOS) structure makes manufacturethereof very easy, which results in an additional advantage that thepower consumption can be reduced. Consequently, it is a common practiceto manufacture the period generating device as an IC in a CMOSstructure.

It will be noted from FIG. 6D that the coincidence signal J is muchdifferent in phase from the reference clock PC. For this reason, anerroneous operation is caused if the coincidence signal J is used todrive the shift registers 18 and 19. Accordingly, it is generallyrequired to generate a period clock which is in phase with the referenceclock PC by stamping out the interval during which the coincidencesignal J is generated with the reference clock PC, that is, by taking anAND of the coincidence signal and a reference clock which is firstinputted to the period generating device during the coincidence signalis generating.

In the example shown in FIG. 7, re-timing means 15 comprising an ANDgate is provided on the output side of the coincidence detecting means13. This re-timing means 15 takes an AND of the coincidence signal J anda reference clock PC which is first inputted to the period generatingdevice during the coincidence signal J is generating, and generates aperiod clock LT shown in FIG. 6E which is synchronized with thereference clock PC. The period clock LT is fed to the shift registers 18and 19 to drive and shift them in synchronism with the reference clockPC.

A miniaturization and a reduction in the power consumption of anapparatus are also demanded in the field of IC testers. To accommodatesuch demand, an attempt is made to manufacture an apparatus by formingcircuits of various portions of the apparatus as an IC. In case theperiod generating device 10 is to be manufactured as an IC, there iscaused, particularly, in the re-timing means 15 a trouble that it isdifficult to match the phase of the reference clock PC to a timing atthe center portion in the interval of the coincidence signal J duringwhich the coincidence signal J is generated. The reason is that thoughit is normal that an IC is formed in a CMOS structure, an IC of CMOSstructure gives an increased time delay to a signal propagating througha circuit element in the IC due to the circuit construction of the CMOSstructure itself. As a result, there is a disadvantage that time delayadjusting means is not available which can be used in the re-timingmeans 15 to match the phase of the reference clock PC to substantiallythe center of the interval during which the coincidence signal J isgenerated.

For example, it is assumed that in a period generating deviceconstructed by circuits of CMOS structure, a delay element 16 isinserted into one signal path to the re-timing means 15 on which thecoincidence signal J is inputted as shown in FIG. 8. In such case, evenif circuit elements (inverters, OR gates, and the like) are used whichgive the minimum time delay to a signal propagating through the circuitelements, a time delay caused by such circuit elements will be equal toor greater than 10 nsec (10×10⁻⁹ sec). Assuming that the reference clockPC has a frequency of 100 MHz for instance, one period of the referenceclock PC is equal to 10 nsec as previously discussed. Accordingly, if atime delay τ₁ of 10 nsec is given to the delay element 16, thecoincidence signal J will be supplied to the re-timing means 15 delayedby a time delay corresponding to one period (10 nsec) of the referenceclock PC. If the time delay τ₁ of the delay element 16 should increasebeyond 10 nsec even slightly, the relationship between the coincidencesignal outputted from the coincidence detecting means 13 and thereference clock PC in the input side of the re-timing means 15 willbecome a bad condition in which the central portion of the coincidencesignal J cannot be stamped out with a reference clock PC, i.e., an ANDof the reference clock PC and the coincidence signal J cannot be takenat the central portion of the coincidence signal J as shown in FIG. 9B.Thus, if the time delay τ₁ of the delay element 16 exceeds one period Tof the reference clock PC, the re-timing means 15 outputs two periodsignals LT and LT' as shown in FIG. 9C, and consequently, there iscaused a disadvantage that the shift registers 18 and 19 will performtheir shift operations twice, or alternatively, the pulse width of theperiod signal LT will be narrowed, resulting in a failure to providereliable shift operations of the shift registers 18 and 19.

Accordingly, it may be contemplated to eliminate the delay element 16.However, in case the delay element 16 is eliminated, the delay time ofthe coincidence signal J comes to be shorter than the pulse width of thereference clock PC. In this case, there is again caused a disadvantagethat two period signals LT and LT' are produced as illustrated in FIG.10.

Alternatively, a method may be contemplated, which utilizes a latchcircuit 17 in place of the delay element 16 as shown in FIG. 11.However, in case the counter 12, the coincidence detecting means 13 andthe latch circuit 17 are manufactured in the form of a CMOS structure,it is very difficult to complete the operations of these circuitelements within a time duration of 5 nsec corresponding to half of theperiod, namely, the pulse width of the reference clock PC. In order toassure the normal operations thereof by the method utilizing the latchcircuit 17, there is no means but to make longer the period of thereference clock PC. However, if the period of the reference clock PC isprolonged, the period with which the period clock LT is generated willincrease, resulting in a disadvantage that the period resolution or theresolution of the period is deteriorated and hence the set resolution ofthe test period for ICs is lowered.

DISCLOSURE OF THE INVENTION

It is an object of the present invention to provide a period generatingdevice which operates in a stable manner without making longer theperiod of reference clock even if the period generating device is formedas an IC in the form of a CMOS structure.

In accordance with the present invention, a reference clock PC isdirectly supplied to a trigger input terminal of each of flip-flopswhich constitute a shift register provided at the previous stage to aperiod memory, and a switching circuit is provided at the previous stageto each flip-flop. The switching circuits are controlled to be switchedin accordance with the presence or absence of a coincidence signal Jsuch that when the coincidence signal J is not outputted, an output ofeach flip-flop is fed back to its own input terminal, whereas when thecoincidence signal J is outputted, an output of the preceding stageflip-flop is transferred to the input terminal of the immediatelysubsequent stage flip-flop, and the individual flip-flops are operatedin synchronism with the reference clock.

With the above arrangement of the present invention, it is only requiredthat a time interval within which the counter 12, the coincidencedetecting means 13 and the latch circuit 17 complete their operations isshorter than a time interval corresponding to one period of thereference clock. Accordingly, as compared with a conventionalarrangement in which the operations thereof must be completed within atime interval corresponding to a half-period of the reference clock PC,the allowable limits of time is doubled. Thus, a period generatingdevice which is manufactured as an IC in the form of a CMOS structurecan be realized.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing a general construction of anembodiment of the period generating device according to the presentinvention;

FIG. 2 is a block diagram showing the detailed construction of a shiftregister used in the embodiment shown in FIG. 1;

FIG. 3 is waveforms for explaining the operation of the shift registershown in FIG. 2;

FIG. 4 is a block diagram showing a general construction of an exampleof the conventional IC tester;

FIG. 5 is a block diagram showing a general construction of an exampleof the period generating device used in a conventional IC tester;

FIG. 6 is waveforms for explaining the operation of the periodgenerating device shown in FIG. 5;

FIG. 7 is a block diagram showing an example of the conventional periodgenerating device provided with re-timing means;

FIG. 8 is a schematic circuit diagram showing an example of there-timing means used in a period generating device used in theconventional IC tester;

FIG. 9 is waveforms for explaining a drawback of the re-timing meansshown in FIG. 8;

FIG. 10 is waveforms for explaining a drawback of the re-timing meansshown in FIG. 8 from which a delay element is eliminated; and

FIG. 11 is a schematic circuit diagram showing an another example of there-timing means used in a period generating device used in theconventional IC tester.

BEST MODE FOR CARRYING OUT THE INVENTION

A period generating device according to an embodiment of the presentinvention will now be described in detail with reference to thedrawings. FIG. 1 shows a general construction of an embodiment of theperiod generating device according to the present invention, and FIG. 2is a block diagram showing a detailed construction of a shift registerused in the embodiment shown in FIG. 1. In this embodiment, a switchingcircuit MUX is provided at the previous stage to each of flip-flops FFconstituting a shift register 18 and at the previous stage to each offlip-flops FF constituting a shift register 19, as shown in FIG. 2. Theshift register 18 operates as a pipeline and is provided at the previousstage to a period memory 11 which stores period data therein, and theshift register 19 also operates as a pipeline and is provided at thesubsequent stage to the period memory 11. While only the previous stageshift register 18 is shown in FIG. 2, it should be understood that thesubsequent stage shift register 19 is also arranged in a similar circuitconstruction.

Each switching circuit MUX has an input terminal A to which an outputsignal IA of an associated flip-flop FF at the immediately subsequentstage is supplied, and to another input terminal B of each switchingcircuit MUX is supplied an output signal IB of an associated flip-flopat the immediately previous stage. Each switching circuit MUX has acontrol terminal EN to which a coincidence signal J outputted fromcoincidence detecting means 13 is supplied. An output terminal O of eachswitching circuit MUX is connected to an input terminal D of anassociated flip-flop FF at the immediately subsequent stage. Inaddition, a reference clock PC in the period generating device isinputted to a trigger input terminal CK of each flip-flop FF.

Each of the switching circuits MUX is switched such that its inputterminal A is connected to its output terminal O when the coincidencesignal J applied to the control terminal EN assumes a logic "L" (lowlevel) and the input terminal B is connected to the output terminal Owhen the coincident signal J assumes a logic "H" (high level).Accordingly, when the coincidence detecting means 13 does not detect acoincidence, the input terminal A of each of the switching circuits MUXis connected to its output terminal O. Under this condition, eachflip-flop FF reads therein its own output even if a reference clock PCis inputted to its trigger input terminal CK. Consequently, the timingset data TS stored in each flip-flop FF and period data read out of theperiod memory 11 are not shifted through the shift registers 18 and 19,respectively.

On the other hand, when the coincidence detecting means 13 detects acoincidence and outputs a logic "H" level, each switching circuit MUX isswitched to a condition in which the input terminal B is connected tothe output terminal O. Under this condition, when a reference clock PCis inputted to the trigger input terminal CK of each flip-flop FF, eachflip-flop FF reads therein an output of the immediately preceding stageflip-flop thereto at a timing of the rise or leading edge of thereference clock PC. As a result, the timing set data TS and the perioddata read out of the period memory 11 are shifted one stage by one stagethrough the flip-flops of the corresponding shift registers 18 and 19,respectively, thereby updating the status of the period data outputtedfrom the shift register 19 and inputted to the coincidence detectingmeans 13.

FIG. 3 shows waveforms for explaining the operation of theabove-described period generating device 10 according to the presentinvention. FIG. 3A shows a waveform of the internal reference clock PCof the period generating device 10, FIG. 3B shows a waveform of thecoincidence signal J, and FIG. 3C shows a waveform of the output signalfrom the last stage flio-flop of the shift register 18 in this example.In accordance with the present invention, assuming that the coincidencesignal J is outputted at a time point delayed by delay time τ₁ from thetiming of the rise of a pulse F among the internal reference clockpulses PC in the period generating device 10, the pulse F coincidingwith the period data, shift operations by the shift registers 18 and 19take place at the timing of the rise of the next reference clock pulse1, whereby the timing set data TS outputted from the last stageflip-flop of the shift register 18 is updated from #F to #2, forinstance. Accordingly, as long as the timing of the rise of thecoincidence signal J is at any time point within a range correspondingto nearly one period from a time point immediately after the rise of thereference clock pulse F to a time point immediately before the rise ofthe immediately subsequent reference clock pulse 1, the input terminalof each switching circuit MUX is switched from A to B if the coincidencesignal J assumes a logic "H" level at the timing of the rise of the nextpulse 1. Consequently, shift operations by the shift registers 18 and 19are certainly effected. In addition, since the reference clock PCapplied to the trigger input terminal CK of each flip-flop FF cannot becut or shortened in pulse width, the shift registers 18 and 19 canoperate in a stable condition.

As described above, in accordance with the present invention, the periodgenerating device is arranged such that the reference clock PC isapplied to at least the shift register 18 provided at the previous stageto the period memory 11, and the respective shift registers operate toshift a signal in response to the reference clock PC only when thecoincidence signal J is applied thereto. Accordingly, a reliableoperation of each shift register is assured if the phase of thecoincidence signal J is close to the phase of the reference clock PC oris delayed by nearly one period. In other words, an allowable limits inthe delay of the coincidence signal J can be made broader (nearlydoubled as compared with the prior art). As a result, even in case thecounter 12 and the coincidence detecting means 13 are formed as an IC ofa CMOS structure which gives an increased delay time to a signalpropagating therethrough, only the sum of the delay times of the counter12 and the coincidence detecting means 13 is required to remain in arange of time which is slightly shorter than one period of the referenceclock PC, and hence a remarkable advantage is obtained that the periodgenerating device 10 arranged to have the shift registers 18 and 19 canbe realized as a circuitry of a CMOS structure.

Further, in the foregoing the present invention has been described withreference to ICs which are a typical example of the semiconductordevices. However, it is needless to say that the present invention isalso applicable to a period generating device used in a semiconductordevice testing apparatus for testing semiconductor devices other thanICs, and the same function and effects can be obtained. In addition,registers at respective stages constituting a shift register may not belimited to flip-flops.

What is claimed is:
 1. A period generating device wherein a periodsignal having a given period is supplied to a pattern generator todetermine the period of a test pattern signal which is applied from saidpattern generator to a semiconductor device to be tested, and the periodof said period signal is defined by timing set data supplied from saidpattern generator, and comprising:a counter for counting a referenceclock; a period memory which has previously stored a plurality of perioddata therein, supplied thereto with said timing set data outputted fromsaid pattern generator as an address signal, and for outputting a perioddata stored at an address which is accessed by said address signal;coincidence detecting means for comparing a count value of said counterwith a period data read out of said period memory and for outputting acoincidence signal upon detection of a coincidence between said countvalue and said period data; and a shift register having registers as aplurality of stages each having stored therein the timing set data to besupplied to said period memory and constituting a pipeline in which thestored timing set data are sequentially shifted one stage by one stageeach time a period signal is generated, said period generating devicefurther comprising:a plurality of switching means each being provided atthe previous stage to each of said registers which constitute said shiftregister; and means for controlling said plurality of switching meanssuch that said switching means are switched to a condition that thetiming set data stored in the previous stage register to each switchingmeans is transferred to the subsequent stage register in synchronismwith the reference clock when said coincidence detecting means outputs acoincidence signal, and to a condition that the timing set data storedin each switching means is fed back to the input terminal of eachswitching means in synchronism with the reference clock when thecoincidence signal is not outputted, whereby the timing set data storedin each register is maintained therein under the condition that thecoincidence signal is not outputted.
 2. A period generating deviceaccording to claim 1 wherein:said plurality of registers constitutingsaid shift register are D-type flip-flops, respectively; each of saidswitching means is a multiplexer having two input terminals, an outputterminal and a control terminal, each of said multiplexers beingarranged such that one of the input terminals is connected to the outputterminal when the coincidence terminal is not supplied to the controlterminal, and the other input terminal is connected to the outputterminal when the coincidence signal is supplied to the controlterminal; each of said flip-flops has a trigger terminal supplied withthe reference clock, an input terminal connected to the output terminalof the previous stage multiplexer, and an output terminal connected toone input terminal of the previous stage multiplexer and to the otherinput terminal of the subsequent stage multiplexer; and the timing setdata is inputted to the other input terminal of the first stagemultiplexer, and the timing set data is outputted to said period memoryfrom the output terminal of the last stage flip-flop.
 3. A periodgenerating device according to claim 1 wherein a second shift registeris provided at the subsequent stage to said period memory, said secondshift register having registers as a plurality of stages each storingtherein the period data read out of said period memory and constitutinga pipeline in which the read-out period data are sequentially shiftedone stage by one stage, and further comprising:a plurality of switchingmeans each being provided at the previous stage to each of saidregisters constituting said second shift register; and means forcontrolling said plurality of switching means such that said switchingmeans are switched to a condition that the period data stored in theprevious stage register to each switching means is transferred to thesubsequent stage register in synchronism with the reference clock whensaid coincidence detecting means outputs a coincidence signal, and to acondition that the period data stored in each switching means is fedback to the input terminal of each switching means in synchronism withthe reference clock when the coincidence signal is not outputted,whereby the period data stored in each register is maintained thereinunder the condition that the coincidence signal is not outputted.
 4. Aperiod generating device according to claim 3 wherein:said plurality ofregisters constituting said second shift register are D-type flip-flops,respectively; each of said switching means provided at the previousstage to each of said registers is a multiplexer having two inputterminals, an output terminal and a control terminal, each of saidmultiplexers being arranged such that one of the input terminals isconnected to the output terminal when the coincidence terminal is notsupplied to the control terminal, and the other input terminal isconnected to the output terminal when the coincidence signal is suppliedto the control terminal; each of said flip-flops has a trigger terminalsupplied with the reference clock, an input terminal connected to theoutput terminal of the previous stage multiplexer, and an outputterminal connected to one input terminal of the previous stagemultiplexer and to the other input terminal of the subsequent stagemultiplexer; and the period data is inputted to the other input terminalof the first stage multiplexer, and the period data is outputted to saidperiod memory from the output terminal of the last stage flip-flop.